The 4A24 is a high resolution, high speed, low cost A-D card for the PC/104 bus.  200 Khz and 500 KHz models are available.  On card EEPROM calibration storage and fully digital zero and span calibration eliminates potentiometers and simplifies circuitry.  A high bandwidth instrumentation amplifier is used for the input.  Input channel scan sequence, averaging option, raw/calibrated data choice, and autozero option are determined by a built-in 1024 entry function table.  Four function table extended multiplexor select addresses are available from the I/O connector for submultiplexing or other functions.  The averaging option in the function table allows A-D data on selected channels to be averaged from 2 to 128 times for noise reduction.  Converted data is placed in a 128K word sample FIFO so that host latency requirements are relaxed.  Conversions can be started by the timer, an external start convert input, or the host processor.  Timed burst conversions (1 to 2^32-1 conversions) can be started by the host or the external start convert input.  The conversion start timer is a 24 bit, 50 MHz programmable divider for high resolution and wide conversion rate range.  The 4A24 can operate in polled or interrupt driven mode.  In polled mode, the data available status of the FIFO is read from a status port and if data as available, the FIFO port can be read.  In the simplest polled mode, the host writes to the FIFO port to start a conversion, polls the status register for the DAV flag and then reads the A-D data from the FIFO port.  In interrupt driven mode, an interrupt is generated when the 128K word FIFO reaches a predetermined count.  At this point the host can do a block I/O read from the FIFO to efficiently transfer the data to the host.  The 4A24 can be programmed to use any of the available PC/104 bus interrupts.  24 general purpose I/O bits are provided. Each I/O bit can be individually programmed to be an input or output.  Optional pullups are provided for all I/O bits.  All main digital logic on the 4A24 is contained in a FPGA to allow field upgradability and customization for special applications.